Abstract
Previous timing analysis methods have assumed that the worst-case
instruction execution time necessarily corresponds to the worst-case
behavior. We show that this assumption is wrong in dynamically
scheduled processors. A cache miss, for example, can in some cases
result in a shorter execution time than a cache hit. Many examples of
such timing anomalies are provided.
We first provide necessary conditions when timing anomalies can show
up and identify what architectural features that may cause such
anomalies. We also show that analyzing the effect of these anomalies
with known techniques results in prohibitive computational
complexities. Instead, we propose some simple code modification
techniques to make it impossible for any anomalies to occur. These
modifications make it possible to estimate WCET by known
techniques. Our evaluation shows that the pessimism imposed by these
techniques is fairly limited; it is less than 27 % for the programs in
our benchmark suite.
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Copyright: 1999 IEEE. See IEEE Computer Society
Online Catalog.
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